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codemirror/mode/verilog/index.html
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210
codemirror/mode/verilog/index.html
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<!doctype html>
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<html>
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<head>
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<meta charset="utf-8">
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<title>CodeMirror: Verilog mode</title>
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<link rel="stylesheet" href="../../lib/codemirror.css">
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<script src="../../lib/codemirror.js"></script>
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<script src="verilog.js"></script>
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<link rel="stylesheet" href="../../doc/docs.css">
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<style>.CodeMirror {border: 2px inset #dee;}</style>
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</head>
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<body>
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<h1>CodeMirror: Verilog mode</h1>
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<form><textarea id="code" name="code">
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/* Verilog demo code */
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// wb_master_model.v ////
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//// ////
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//// This file is part of the SPI IP core project ////
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//// http://www.opencores.org/projects/spi/ ////
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//// ////
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//// Author(s): ////
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//// - Simon Srot (simons@opencores.org) ////
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//// ////
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//// Based on: ////
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//// - i2c/bench/verilog/wb_master_model.v ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
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parameter dwidth = 32;
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parameter awidth = 32;
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input clk, rst;
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output [awidth -1:0] adr;
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input [dwidth -1:0] din;
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output [dwidth -1:0] dout;
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output cyc, stb;
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output we;
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output [dwidth/8 -1:0] sel;
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input ack, err, rty;
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// Internal signals
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reg [awidth -1:0] adr;
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reg [dwidth -1:0] dout;
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reg cyc, stb;
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reg we;
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reg [dwidth/8 -1:0] sel;
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reg [dwidth -1:0] q;
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// Memory Logic
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initial
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begin
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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cyc = 1'b0;
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stb = 1'bx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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#1;
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end
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// Wishbone write cycle
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task wb_write;
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input delay;
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integer delay;
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input [awidth -1:0] a;
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input [dwidth -1:0] d;
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begin
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// wait initial delay
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repeat(delay) @(posedge clk);
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// assert wishbone signal
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#1;
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adr = a;
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dout = d;
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cyc = 1'b1;
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stb = 1'b1;
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we = 1'b1;
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sel = {dwidth/8{1'b1}};
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@(posedge clk);
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// wait for acknowledge from slave
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while(~ack) @(posedge clk);
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// negate wishbone signals
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#1;
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cyc = 1'b0;
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stb = 1'bx;
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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end
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endtask
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// Wishbone read cycle
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task wb_read;
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input delay;
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integer delay;
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input [awidth -1:0] a;
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output [dwidth -1:0] d;
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begin
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// wait initial delay
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repeat(delay) @(posedge clk);
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// assert wishbone signals
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#1;
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adr = a;
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dout = {dwidth{1'bx}};
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cyc = 1'b1;
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stb = 1'b1;
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we = 1'b0;
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sel = {dwidth/8{1'b1}};
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@(posedge clk);
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// wait for acknowledge from slave
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while(~ack) @(posedge clk);
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// negate wishbone signals
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#1;
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cyc = 1'b0;
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stb = 1'bx;
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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d = din;
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end
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endtask
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// Wishbone compare cycle (read data from location and compare with expected data)
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task wb_cmp;
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input delay;
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integer delay;
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input [awidth -1:0] a;
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input [dwidth -1:0] d_exp;
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begin
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wb_read (delay, a, q);
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if (d_exp !== q) begin
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$display("\n--- ERROR: At address 0x%0x, got 0x%0x, expected 0x%0x at time %t", a, q, d_exp, $time);
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$stop;
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end
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end
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endtask
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endmodule
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</textarea></form>
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<script>
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var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
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lineNumbers: true,
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mode: "text/x-verilog"
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});
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</script>
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<p>Simple mode that tries to handle Verilog-like languages as well as it
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can. Takes one configuration parameters: <code>keywords</code>, an
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object whose property names are the keywords in the language.</p>
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<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
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</body>
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</html>
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182
codemirror/mode/verilog/verilog.js
vendored
Normal file
182
codemirror/mode/verilog/verilog.js
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@@ -0,0 +1,182 @@
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CodeMirror.defineMode("verilog", function(config, parserConfig) {
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var indentUnit = config.indentUnit,
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keywords = parserConfig.keywords || {},
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blockKeywords = parserConfig.blockKeywords || {},
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atoms = parserConfig.atoms || {},
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hooks = parserConfig.hooks || {},
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multiLineStrings = parserConfig.multiLineStrings;
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var isOperatorChar = /[&|~><!\)\(*#%@+\/=?\:;}{,\.\^\-\[\]]/;
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var curPunc;
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function tokenBase(stream, state) {
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var ch = stream.next();
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if (hooks[ch]) {
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var result = hooks[ch](stream, state);
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if (result !== false) return result;
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}
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if (ch == '"') {
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state.tokenize = tokenString(ch);
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return state.tokenize(stream, state);
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}
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if (/[\[\]{}\(\),;\:\.]/.test(ch)) {
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curPunc = ch;
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return null;
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}
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if (/[\d']/.test(ch)) {
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stream.eatWhile(/[\w\.']/);
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return "number";
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}
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if (ch == "/") {
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if (stream.eat("*")) {
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state.tokenize = tokenComment;
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return tokenComment(stream, state);
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}
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if (stream.eat("/")) {
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stream.skipToEnd();
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return "comment";
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}
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}
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if (isOperatorChar.test(ch)) {
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stream.eatWhile(isOperatorChar);
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return "operator";
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}
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stream.eatWhile(/[\w\$_]/);
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var cur = stream.current();
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if (keywords.propertyIsEnumerable(cur)) {
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if (blockKeywords.propertyIsEnumerable(cur)) curPunc = "newstatement";
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return "keyword";
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}
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if (atoms.propertyIsEnumerable(cur)) return "atom";
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return "variable";
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}
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function tokenString(quote) {
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return function(stream, state) {
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var escaped = false, next, end = false;
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while ((next = stream.next()) != null) {
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if (next == quote && !escaped) {end = true; break;}
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escaped = !escaped && next == "\\";
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}
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if (end || !(escaped || multiLineStrings))
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state.tokenize = tokenBase;
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return "string";
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};
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}
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function tokenComment(stream, state) {
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var maybeEnd = false, ch;
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while (ch = stream.next()) {
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if (ch == "/" && maybeEnd) {
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state.tokenize = tokenBase;
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break;
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}
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maybeEnd = (ch == "*");
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}
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return "comment";
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}
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function Context(indented, column, type, align, prev) {
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this.indented = indented;
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this.column = column;
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this.type = type;
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this.align = align;
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this.prev = prev;
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}
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function pushContext(state, col, type) {
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return state.context = new Context(state.indented, col, type, null, state.context);
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}
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function popContext(state) {
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var t = state.context.type;
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if (t == ")" || t == "]" || t == "}")
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state.indented = state.context.indented;
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return state.context = state.context.prev;
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}
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// Interface
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return {
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startState: function(basecolumn) {
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return {
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tokenize: null,
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context: new Context((basecolumn || 0) - indentUnit, 0, "top", false),
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indented: 0,
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startOfLine: true
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};
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},
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token: function(stream, state) {
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var ctx = state.context;
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if (stream.sol()) {
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if (ctx.align == null) ctx.align = false;
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state.indented = stream.indentation();
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state.startOfLine = true;
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}
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if (stream.eatSpace()) return null;
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curPunc = null;
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var style = (state.tokenize || tokenBase)(stream, state);
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if (style == "comment" || style == "meta") return style;
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if (ctx.align == null) ctx.align = true;
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if ((curPunc == ";" || curPunc == ":") && ctx.type == "statement") popContext(state);
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else if (curPunc == "{") pushContext(state, stream.column(), "}");
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else if (curPunc == "[") pushContext(state, stream.column(), "]");
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else if (curPunc == "(") pushContext(state, stream.column(), ")");
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else if (curPunc == "}") {
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while (ctx.type == "statement") ctx = popContext(state);
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if (ctx.type == "}") ctx = popContext(state);
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while (ctx.type == "statement") ctx = popContext(state);
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}
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else if (curPunc == ctx.type) popContext(state);
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else if (ctx.type == "}" || ctx.type == "top" || (ctx.type == "statement" && curPunc == "newstatement"))
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pushContext(state, stream.column(), "statement");
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state.startOfLine = false;
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return style;
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},
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indent: function(state, textAfter) {
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if (state.tokenize != tokenBase && state.tokenize != null) return 0;
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var firstChar = textAfter && textAfter.charAt(0), ctx = state.context, closing = firstChar == ctx.type;
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if (ctx.type == "statement") return ctx.indented + (firstChar == "{" ? 0 : indentUnit);
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else if (ctx.align) return ctx.column + (closing ? 0 : 1);
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else return ctx.indented + (closing ? 0 : indentUnit);
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},
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electricChars: "{}"
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};
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});
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(function() {
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function words(str) {
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var obj = {}, words = str.split(" ");
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for (var i = 0; i < words.length; ++i) obj[words[i]] = true;
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return obj;
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}
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var verilogKeywords = "always and assign automatic begin buf bufif0 bufif1 case casex casez cell cmos config " +
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"deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule " +
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"endprimitive endspecify endtable endtask event for force forever fork function generate genvar highz0 " +
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"highz1 if ifnone incdir include initial inout input instance integer join large liblist library localparam " +
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"macromodule medium module nand negedge nmos nor noshowcancelled not notif0 notif1 or output parameter pmos " +
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"posedge primitive pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect rcmos real realtime " +
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"reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared showcancelled signed small specify specparam " +
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"strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg " +
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"unsigned use vectored wait wand weak0 weak1 while wire wor xnor xor";
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var verilogBlockKeywords = "begin bufif0 bufif1 case casex casez config else end endcase endconfig endfunction " +
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"endgenerate endmodule endprimitive endspecify endtable endtask for forever function generate if ifnone " +
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"macromodule module primitive repeat specify table task while";
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function metaHook(stream) {
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stream.eatWhile(/[\w\$_]/);
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return "meta";
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}
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CodeMirror.defineMIME("text/x-verilog", {
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name: "verilog",
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keywords: words(verilogKeywords),
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blockKeywords: words(verilogBlockKeywords),
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atoms: words("null"),
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hooks: {"`": metaHook, "$": metaHook}
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});
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||||
}());
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Reference in New Issue
Block a user